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Freescale Semiconductor /MKM34Z7 /NVIC /NVIC_ICER

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Interpret as NVIC_ICER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CLRENA0 0 (0)CLRENA1 0 (0)CLRENA2 0 (0)CLRENA3 0 (0)CLRENA4 0 (0)CLRENA5 0 (0)CLRENA6 0 (0)CLRENA7 0 (0)CLRENA8 0 (0)CLRENA9 0 (0)CLRENA10 0 (0)CLRENA11 0 (0)CLRENA12 0 (0)CLRENA13 0 (0)CLRENA14 0 (0)CLRENA15 0 (0)CLRENA16 0 (0)CLRENA17 0 (0)CLRENA18 0 (0)CLRENA19 0 (0)CLRENA20 0 (0)CLRENA21 0 (0)CLRENA22 0 (0)CLRENA23 0 (0)CLRENA24 0 (0)CLRENA25 0 (0)CLRENA26 0 (0)CLRENA27 0 (0)CLRENA28 0 (0)CLRENA29 0 (0)CLRENA30 0 (0)CLRENA31

CLRENA0=0, CLRENA19=0, CLRENA6=0, CLRENA13=0, CLRENA31=0, CLRENA30=0, CLRENA8=0, CLRENA11=0, CLRENA24=0, CLRENA29=0, CLRENA4=0, CLRENA16=0, CLRENA14=0, CLRENA5=0, CLRENA28=0, CLRENA22=0, CLRENA12=0, CLRENA7=0, CLRENA26=0, CLRENA25=0, CLRENA20=0, CLRENA17=0, CLRENA18=0, CLRENA27=0, CLRENA10=0, CLRENA23=0, CLRENA3=0, CLRENA21=0, CLRENA15=0, CLRENA9=0, CLRENA2=0, CLRENA1=0

Description

Interrupt Clear Enable Register

Fields

CLRENA0

DMA channel 0 transfer complete interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 0 transfer complete interrupt disabled

1 (1): write: disable DMA channel 0 transfer complete interrupt; read: DMA channel 0 transfer complete interrupt enabled
CLRENA1

DMA channel 1 transfer complete interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 1 transfer complete interrupt disabled

1 (1): write: disable DMA channel 1 transfer complete interrupt; read: DMA channel 1 transfer complete interrupt enabled
CLRENA2

DMA channel 2 transfer complete interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 2 transfer complete interrupt disabled

1 (1): write: disable DMA channel 2 transfer complete interrupt; read: DMA channel 2 transfer complete interrupt enabled
CLRENA3

DMA channel 3 transfer complete interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 3 transfer complete interrupt disabled

1 (1): write: disable DMA channel 3 transfer complete interrupt; read: DMA channel 3 transfer complete interrupt enabled
CLRENA4

Serial Peripheral Interface 0/1 interrupt clear-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 0/1 interrupt disabled

1 (1): write: disable Serial Peripheral Interface 0/1 interrupt; read: Serial Peripheral Interface 0/1 interrupt enabled
CLRENA5

Programmable Delay Block 0 interrupt clear-enable bit

0 (0): write: no effect; read: Programmable Delay Block 0 interrupt disabled

1 (1): write: disable Programmable Delay Block 0 interrupt; read: Programmable Delay Block 0 interrupt enabled
CLRENA6

Low-voltage detect, low-voltage warning interrupt clear-enable bit

0 (0): write: no effect; read: Low-voltage detect, low-voltage warning interrupt disabled

1 (1): write: disable Low-voltage detect, low-voltage warning interrupt; read: Low-voltage detect, low-voltage warning interrupt enabled
CLRENA7

Quad Timer Channel 0 interrupt clear-enable bit

0 (0): write: no effect; read: Quad Timer Channel 0 interrupt disabled

1 (1): write: disable Quad Timer Channel 0 interrupt; read: Quad Timer Channel 0 interrupt enabled
CLRENA8

Quad Timer Channel 1 interrupt clear-enable bit

0 (0): write: no effect; read: Quad Timer Channel 1 interrupt disabled

1 (1): write: disable Quad Timer Channel 1 interrupt; read: Quad Timer Channel 1 interrupt enabled
CLRENA9

Quad Timer Channel 2 interrupt clear-enable bit

0 (0): write: no effect; read: Quad Timer Channel 2 interrupt disabled

1 (1): write: disable Quad Timer Channel 2 interrupt; read: Quad Timer Channel 2 interrupt enabled
CLRENA10

Quad Timer Channel 3 interrupt clear-enable bit

0 (0): write: no effect; read: Quad Timer Channel 3 interrupt disabled

1 (1): write: disable Quad Timer Channel 3 interrupt; read: Quad Timer Channel 3 interrupt enabled
CLRENA11

PIT0/PIT1 interrupt clear-enable bit

0 (0): write: no effect; read: PIT0/PIT1 interrupt disabled

1 (1): write: disable PIT0/PIT1 interrupt; read: PIT0/PIT1 interrupt enabled
CLRENA12

Low Leakage Wakeup interrupt clear-enable bit

0 (0): write: no effect; read: Low Leakage Wakeup interrupt disabled

1 (1): write: disable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
CLRENA13

Command complete and read collision interrupt clear-enable bit

0 (0): write: no effect; read: Command complete and read collision interrupt disabled

1 (1): write: disable Command complete and read collision interrupt; read: Command complete and read collision interrupt enabled
CLRENA14

CMP0/CMP1/CMP2 interrupt clear-enable bit

0 (0): write: no effect; read: CMP0/CMP1/CMP2 interrupt disabled

1 (1): write: disable CMP0/CMP1/CMP2 interrupt; read: CMP0/CMP1/CMP2 interrupt enabled
CLRENA15

Segment LCD interrupt clear-enable bit

0 (0): write: no effect; read: Segment LCD interrupt disabled

1 (1): write: disable Segment LCD interrupt; read: Segment LCD interrupt enabled
CLRENA16

Analog-to-Digital Converter interrupt clear-enable bit

0 (0): write: no effect; read: Analog-to-Digital Converter interrupt disabled

1 (1): write: disable Analog-to-Digital Converter interrupt; read: Analog-to-Digital Converter interrupt enabled
CLRENA17

PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt clear-enable bit

0 (0): write: no effect; read: PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt disabled

1 (1): write: disable PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt; read: PORTA,PORTB,PORTC,PORTD,PORTE,PORTF,PORTH,PORTI,PORTJ,PORTK,PORTL,PORTM interrupt enabled
CLRENA18

RNGA interrupt clear-enable bit

0 (0): write: no effect; read: RNGA interrupt disabled

1 (1): write: disable RNGA interrupt; read: RNGA interrupt enabled
CLRENA19

UART0/UART1/UART2/UART3 interrupt clear-enable bit

0 (0): write: no effect; read: UART0/UART1/UART2/UART3 interrupt disabled

1 (1): write: disable UART0/UART1/UART2/UART3 interrupt; read: UART0/UART1/UART2/UART3 interrupt enabled
CLRENA20

Memory Mapped Arithmetic Unit interrupt clear-enable bit

0 (0): write: no effect; read: Memory Mapped Arithmetic Unit interrupt disabled

1 (1): write: disable Memory Mapped Arithmetic Unit interrupt; read: Memory Mapped Arithmetic Unit interrupt enabled
CLRENA21

AFE Channel 0 interrupt clear-enable bit

0 (0): write: no effect; read: AFE Channel 0 interrupt disabled

1 (1): write: disable AFE Channel 0 interrupt; read: AFE Channel 0 interrupt enabled
CLRENA22

AFE Channel 1 interrupt clear-enable bit

0 (0): write: no effect; read: AFE Channel 1 interrupt disabled

1 (1): write: disable AFE Channel 1 interrupt; read: AFE Channel 1 interrupt enabled
CLRENA23

AFE Channel 2 interrupt clear-enable bit

0 (0): write: no effect; read: AFE Channel 2 interrupt disabled

1 (1): write: disable AFE Channel 2 interrupt; read: AFE Channel 2 interrupt enabled
CLRENA24

AFE Channel 3 interrupt clear-enable bit

0 (0): write: no effect; read: AFE Channel 3 interrupt disabled

1 (1): write: disable AFE Channel 3 interrupt; read: AFE Channel 3 interrupt enabled
CLRENA25

IRTC interrupt interrupt clear-enable bit

0 (0): write: no effect; read: IRTC interrupt interrupt disabled

1 (1): write: disable IRTC interrupt interrupt; read: IRTC interrupt interrupt enabled
CLRENA26

I2C0/I2C1 interrupt clear-enable bit

0 (0): write: no effect; read: I2C0/I2C1 interrupt disabled

1 (1): write: disable I2C0/I2C1 interrupt; read: I2C0/I2C1 interrupt enabled
CLRENA27

LPUART0 status and error interrupt clear-enable bit

0 (0): write: no effect; read: LPUART0 status and error interrupt disabled

1 (1): write: disable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled
CLRENA28

Multipurpose Clock Generator interrupt clear-enable bit

0 (0): write: no effect; read: Multipurpose Clock Generator interrupt disabled

1 (1): write: disable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled
CLRENA29

EWM/WDOG interrupt clear-enable bit

0 (0): write: no effect; read: EWM/WDOG interrupt disabled

1 (1): write: disable EWM/WDOG interrupt; read: EWM/WDOG interrupt enabled
CLRENA30

Low-Power Timer interrupt clear-enable bit

0 (0): write: no effect; read: Low-Power Timer interrupt disabled

1 (1): write: disable Low-Power Timer interrupt; read: Low-Power Timer interrupt enabled
CLRENA31

XBAR interrupt clear-enable bit

0 (0): write: no effect; read: XBAR interrupt disabled

1 (1): write: disable XBAR interrupt; read: XBAR interrupt enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data